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? 2012 microchip technology inc. ds25154a-page 1 mcp47a1 features: ?6-bit dac - 65 taps: 64 resistors with taps to full-scale and zero-scale (wiper code 00h to 40h) ?v ref pull-down resistance: 20 k ? (typical) ?v out voltage range -v ss to v ref ?i 2 c ? protocol - supports smbus 2.0 write byte/word protocol formats - supports smbus 2.0 read byte/word protocol formats - slave addresses: 5ch and 7ch ? brown-out reset protection (1.5v typical) ? power-on default wiper setting (mid-scale) ? low-power operation: 90 a static current (typical) ? wide operating voltage range: - 1.8v to 5.5v ? low tempco: 15 ppm (typical) ? 100 khz (typical) bandwidth (-3 db) operation ? extended temperature range (-40c to +125c) ? small packages, sc70-6 ? lead free (pb-free) package applications ? set point or offset trimming ? cost-sensitive mechanical trim pot replacement package types device block diagram description the mcp47a1 devices are volatile, 6-bit digital potentiometers with a buffered output. the wiper setting is controlled through an i 2 c serial interface. the i 2 c slave addresses of ?010 1110? and ?011 1110? are supported. mcp47a1 sc70-6 4 1 2 3 6 v ref sda v dd v ss scl 5 v out a w b v dd v ss scl v out b wiper register (r ab = 20k ? ) sda v ref 2-wire interface and control logic power-up and brown-out control a 6-bit volatile dac with command code
mcp47a1 ds25154a-page 2 ? 2012 microchip technology inc. device features device interface # of taps # of resistors v ref resistance (k ? ) data value range por/bor value i 2 c slave address v dd operating range v out range package(s) mcp47a1 i 2 c 65 64 20 00h - 40h 20h 5ch, 7ch 1.8v ( 1 ) to 5.5v v ss to v ref sc70-6 mcp47da1 ( 2 ) i 2 c 65 64 30 00h - 7fh 40h 5ch, 7ch 1.8v ( 1 ) to 5.5v 1/3 v ref to 2/3 v ref sc70-6, sot-23-6 mcp4706 i 2 c 256 256 210 00h - ffh 7fh cxh ( 3 ) 2.7v to 5.5v v ss to v dd or v ss to v ref ( 5 ) sot-23-6, dfn-6 (2x2) mcp4716 i 2 c 1024 1024 210 000h - 3ffh 1ffh cxh ( 3 ) 2.7v to 5.5v v ss to v dd or v ss to v ref ( 5 ) sot-23-6, dfn-6 (2x2) mcp4726 i 2 c 4096 4096 210 000h - fffh 3ffh cxh ( 3 ) 2.7v to 5.5v v ss to v dd or v ss to v ref ( 5 ) sot-23-6, dfn-6 (2x2) mcp4725 i 2 c 4096 4096 n.a. 000h - fffh 3ffh cxh ( 4 ) 2.7v to 5.5v v ss to v dd sot-23-6 note 1: analog characteristics only tested from 2.7v to 5.5v. 2: refer to mcp47da1 data sheet (ds25118). 3: the a2:a0 bits are determined by device ordered. 4: the a2 and a1 bits are determined by device ordered and a0 is determined by the state of the a0 pin. 5: user programmable.
? 2012 microchip technology inc. ds25154a-page 3 mcp47a1 1.0 electrical characteristics absolute maximum ratings ? voltage on v dd with respect to v ss .......................................................................................................... 0.6v to +7.0v voltage on scl, and sda with respect to v ss ..................................................................................................... -0.6v to v dd + 0.3v voltage on all other pins (v out and v ref ) with respect to v ss ..................................................................... -0.3v to v dd + 0.3v input clamp current, i ik (v i < 0, v i > v dd ) ............................................................................................................ 20 ma output clamp current, i ok (v o < 0 or v o > v dd ).................................................................................................. 20 ma maximum output current sunk by any output pin ................................................................................. ................. 25 ma maximum output current sourced by any output pin .............................................................................. .............. 25 ma maximum current out of v ss pin .......................................................................................................................... 100 ma maximum current into v dd pin ........................................................................................................................... .. 100 ma maximum current into v ref pin........................................................................................................................... .. 250 ua maximum current sourced by v out pin ................................................................................................................. 40 ma maximum current sunk by v ref pin ....................................................................................................................... 40 m a package power dissipation (t a = +50c, t j = +150c) sc70-6 ......................................................................................................................... ............................ 480 mw storage temperature ............................................................................................................ .................. -65c to +150c ambient temperature with power applied ........................................................................................ ...... -40c to +125c esd protection on all pins .................................................................................................... ...................... ?? 6 kv (hbm) ............................................................................................................................... ...................................... ?? 400v (mm) ??????????????????????????????????????????????????????????????? ??????????????????????????????????????????????????????????????? ???????????????????????????????????????????????????? ??? 1.5 kv (cdm) latchup (jedec jesd78a) at +125c .............................................................................................. ............... 100 ma soldering temperature of leads (10 seconds) .................................................................................... .................. +300c maximum junction temperature (t j ) .................................................................................................................. +150c ? notice: stresses above those listed under ?maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
mcp47a1 ds25154a-page 4 ? 2012 microchip technology inc. ac/dc characteristics dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to +5.5v. c l = 1 nf, r l = 5 k ? . typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions supply voltage v dd 2.7 ? 5.5 v analog characteristics specified 1.8 ? 5.5 v digital characteristics specified v dd start voltage to ensure wiper to default reset state v bor ? ? 1.65 v ram retention voltage (v ram ) < v bor v dd rise rate to ensure power-on reset v ddrr note 5 v/ms delay after device exits the reset state (v dd > v bor ) to digital interface active t bord ??1s delay after device exits the reset state (v dd > v bor ) to v out valid t outv 20 s within 0.5 lsb of v ref / 2 (for default por/bor wiper value). supply current ? ( note 6 ) i dd ? 130 220 a serial interface active, write all 0 ?s to volatile wiper, no load on v out v dd = 5.5v, v ref = v dd , f scl = 400 khz ? 90 130 a serial interface inactive (static), (stop condition, scl = sda = v ih ), no load on v out wiper = 0, v dd = 5.5v, v ref = v dd v ref input range v ref 1?v dd v note 7 note 1: resistance is defined as the resistance between the v ref pin and the v ss pin. 2: inl and dnl are measured at v out from code = 00h (zero-scale) through code = 3fh (full-scale - 1). 3: this specification by design. 4: nonlinearity is affected by wiper resistance (r w ), which changes significantly over voltage and temperature. 5: por/bor is not rate dependent. 6: supply current is independent of v ref current. 7: see section 7.1.3 .
? 2012 microchip technology inc. ds25154a-page 5 mcp47a1 output amplifier minimum output voltage v out(min) ?v ss ? v device output minimum drive maximum output voltage v out(max) ?v ref ? v device output maximum drive phase margin pm ? 66 ? degree () c l = 400 pf, r l = ? slew rate sr ? 0.55 ? v/s short circuit current i sc 51524ma settling time t settling ?15?s external reference (v ref ) ( note 3 ) input capacitance c vref ?7?pf total harmonic distortion thd ?-73?dbv ref = 1.65v 0.1v, frequency = 1 khz dynamic performance ( note 3 ) major code transition glitch ? 45 ? nv-s 1 lsb change around major carry (20h to 1fh) digital feedthrough ?<10?nv-s ac/dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to +5.5v. c l = 1 nf, r l = 5 k ? . typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between the v ref pin and the v ss pin. 2: inl and dnl are measured at v out from code = 00h (zero-scale) through code = 3fh (full-scale - 1). 3: this specification by design. 4: nonlinearity is affected by wiper resistance (r w ), which changes significantly over voltage and temperature. 5: por/bor is not rate dependent. 6: supply current is independent of v ref current. 7: see section 7.1.3 .
mcp47a1 ds25154a-page 6 ? 2012 microchip technology inc. resistance ( 20%) r vref 16.0 20 24.0 k ? note 1 , resolution n 65 taps no missing codes step resistance r s ?r vref / 64 ? ? note 3 nominal resistance te m p c o ? r vref / ? t ? 50 ? ppm/c t a = -20c to +70c ? 100 ? ppm/c t a = -40c to +85c ? 150 ? ppm/c t a = -40c to +125c ratiometeric te m p c o ? v out / ? t ? 15 ? ppm/c code = midscale (20h) v out accuracy 0.72 0.75 0.78 v v ref = 1.5v, code = 20h v out load l voutr 5??k ? resistive load l voutc ? ? 1 nf capacitive load maximum current through terminal (v ref ) note 3 i vref ??345av ref = 5.5v leakage current into v ref i l ? 100 ? na v ref = v ss full-scale error (code = 40h) v fse -1 0.35 +1 lsb v ref = v dd zero-scale error (code = 00h) v zse -0.75 0.35 +0.75 lsb v ref = v dd v out integral nonlinearity inl -1 0.25 +1 lsb note 2 , v ref = v dd v out differential nonlinearity dnl -0.5 0.25 +0.5 lsb note 2 , v ref = v dd bandwidth -3 db bw ? 100 ? khz v dd = 5.0v, v ref = 3.0v 2.0v, code = 20h capacitance (v ref ) c ref ? 75 ? pf f =1 mhz, code = full-scale ac/dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to +5.5v. c l = 1 nf, r l = 5 k ? . typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between the v ref pin and the v ss pin. 2: inl and dnl are measured at v out from code = 00h (zero-scale) through code = 3fh (full-scale - 1). 3: this specification by design. 4: nonlinearity is affected by wiper resistance (r w ), which changes significantly over voltage and temperature. 5: por/bor is not rate dependent. 6: supply current is independent of v ref current. 7: see section 7.1.3 .
? 2012 microchip technology inc. ds25154a-page 7 mcp47a1 digital inputs/outputs (sda, sck) schmitt trigger high input threshold v ih 0.7 v d d ?? v1.8v ? v dd ? 5.5v schmitt trigger low input threshold v il -0.5 ? 0.3v d d v1.8v ? v dd ? 5.5v hysteresis of schmitt trigger inputs ( note 3 ) v hys n.a. ? ? v sda and scl 100 khz v dd < 2.0v n.a. ? ? v v dd ? 2.0v 0.1 v d d ?? v 400 khz v dd < 2.0v 0.05 v dd ?? v v dd ? 2.0v output low voltage (sda) v ol v ss ?0.4 vv dd ? 2.0v, i ol = 3 ma v ss ?0.2v d d vv dd < 2.0v, i ol = 1 ma input leakage current i il -1 ? 1 a v ref = v dd and v ref = v ss pin capacitance c in , c out ?10?pff c = 400 khz ram (wiper) value value range n 0h ? 40h hex wiper por/bor value n por/bor 20h hex power requirements power supply sensitivity pss ? 0.0015 0.003 5 %/% v ref = v dd , code = 20h ac/dc characteristics (continued) dc characteristics standard operating conditions (unless otherwise specified) operating temperature ?40c ? t a ? +125c (extended) all parameters apply across the specified operating ranges unless noted. v dd = +2.7v to +5.5v. c l = 1 nf, r l = 5 k ? . typical specifications represent values for v dd = 5.5v, t a = +25c. parameters sym min typ max units conditions note 1: resistance is defined as the resistance between the v ref pin and the v ss pin. 2: inl and dnl are measured at v out from code = 00h (zero-scale) through code = 3fh (full-scale - 1). 3: this specification by design. 4: nonlinearity is affected by wiper resistance (r w ), which changes significantly over voltage and temperature. 5: por/bor is not rate dependent. 6: supply current is independent of v ref current. 7: see section 7.1.3 .
mcp47a1 ds25154a-page 8 ? 2012 microchip technology inc. 1.1 i 2 c mode timing waveforms and requirements figure 1-1: i 2 c bus start/stop bits timing waveforms. figure 1-2: i 2 c bus data timing. table 1-1: i 2 c bus start/stop bits requirements 91 93 scl sda start condition stop condition 90 92 i 2 c ac characteristics standard operating conditions (unless otherwise specified) operating temperature ?40 ? c ? t a ? +125 ? c (extended) operating voltage v dd range is described in section 2.0 ?typical performance curves? param. no. symbol characteristic min max units conditions f scl standard mode 0 100 khz c b = 400 pf, 1.8v - 5.5v fast mode 0 400 khz c b = 400 pf, 2.7v - 5.5v d102 cb bus capacitive loading 100 khz mode ? 400 pf 400 khz mode ? 400 pf 90 t su : sta start condition 100 khz mode 4700 ? ns only relevant for repeated start condition setup time 400 khz mode 600 ? ns 91 t hd : sta start condition 100 khz mode 4000 ? ns after this period, the first clock pulse is generated hold time 400 khz mode 600 ? ns 92 t su : sto stop condition 100 khz mode 4000 ? ns setup time 400 khz mode 600 ? ns 93 t hd : sto stop condition 100 khz mode 4000 ? ns hold time 400 khz mode 600 ? ns note: refer to specification d102 (cb) for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 scl sda in sda out
? 2012 microchip technology inc. ds25154a-page 9 mcp47a1 table 1-2: i 2 c bus data requirements (slave mode) i 2 c ac characteristics standard operating conditions (unless otherwise specified) operating temperature ?40 ? c ? t a ? +125 ? c (extended) operating voltage v dd range is described in ac/dc characteristics parame- ter no. sym characteristic min max units conditions 100 t high clock high time 100 khz mode 4000 ? ns 1.8v-5.5v 400 khz mode 600 ? ns 2.7v-5.5v 101 t low clock low time 100 khz mode 4700 ? ns 1.8v-5.5v 400 khz mode 1300 ? ns 2.7v-5.5v 102a ( 5 ) t rscl scl rise time 100 khz mode ? 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1cb 300 ns 102b ( 5 ) t rsda sda rise time 100 khz mode ? 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1cb 300 ns 103a ( 5 ) t fscl scl fall time 100 khz mode ? 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1cb 40 ns 103b ( 5 ) t fsda sda fall time 100 khz mode ? 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1cb ( 5 ) 300 ns 106 t hd : dat data input hold time 100 khz mode 0 ? ns 1.8v-5.5v ( note 6 ) 400 khz mode 0 ? ns 2.7v-5.5v ( note 6 ) 107 t su : dat data input setup time 100 khz mode 250 ? ns note 5 400 khz mode 100 ? ns 109 t aa output valid from clock 100 khz mode ? 3450 ns note 5 400 khz mode ? 900 ns 110 t buf bus free time 100 khz mode 4700 ? ns time the bus must be free before a new transmission can start 400 khz mode 1300 ? ns t sp input filter spike suppression (sda and scl) 100 khz mode ? 50 ns philips spec states n.a. 400 khz mode ? 50 ns note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast-mode (400 khz) i 2 c-bus device can be used in a standard-mode (100 khz) i 2 c-bus system, but the requirement tsu; dat ? 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max.+tsu;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c bus specification) before the scl line is released. 3: the mcp47a1 device must provide a data hold time to bridge the undefined part between v ih and v il of the falling edge of the scl signal. this specification is not a part of the i 2 c specification, but must be tested in order to guarantee that the output data will meet the setup and hold specifications for the receiving device. 4: use c b in pf for the calculations. 5: not tested. 6: a master transmitter must provide a delay to ensure that difference between sda and scl fall times do not unintentionally create a start or stop condition.
mcp47a1 ds25154a-page 10 ? 2012 microchip technology inc. temperature characteristics electrical specifications: unless otherwise indicated, v dd = +2.7v to +5.5v, v ss = gnd. parameters sym min typ max units conditions temperature ranges specified temperature range t a -40 ? +125 c operating temperature range t a -40 ? +125 c storage temperature range t a -65 ? +150 c thermal package resistances thermal resistance, 6l-sc70 ? ja ?207?c/w note 1 note 1: package power dissipation (p dis ) is calculated as follows: p dis = (t j - t a ) / ? ja , where: t j = junction temperature, t a = ambient temperature.
? 2012 microchip technology inc. ds25154a-page 11 mcp47a1 2.0 typical performance curves note: unless otherwise indicated, t a = +25c, v dd = v ref = 5v, v ss = 0v, r l = 5 k ? , c l = 1 nf. figure 2-1: inl vs. code (00h to 3fh) and temperature. v dd = 5.5v, v ref = 5.5v, 2.7v, 1.8v, and 1.0v. figure 2-2: inl vs. code (00h to 3fh) and temperature. v dd = 2.7v, v ref = 2.7v, 1.8v, and 1.0v. figure 2-3: inl vs. code (00h to 3fh) and temperature. v dd = 2.0v, v ref = 2.0v, 1.8v, and 1.0v. figure 2-4: inl vs. code (00h to 3fh) and temperature. v dd = 1.8v, v ref = 1.6v, and 1.0v. note 1: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 0.25 0.00 0.25 0.50 0.75 1.00 inl (lsb) 1.00 0.75 0.50 0 8 16 24 32 40 48 56 64 dac wiper code 40c 5.5v +25c 5.5v +85c 5.5v +125c 5.5v 40c 2.7v +25c 2.7v +85c 2.7v +125c 2.7v 40c 1.8v +25c 1.8v +85c 1.8v +125c 1.8v 40c 1.0v +25c 1.0v +85c 1.0v +125c 1.0v typical device 0.25 0.00 0.25 0.50 0.75 1.00 inl (lsb) 1.00 0.75 0.50 0 8 16 24 32 40 48 56 64 dac wiper code 40c 2.7v +25c 2.7v +85c 2.7v +125c 2.7v 40c 1.8v +25c 1.8v +85c 1.8v +125c 1.8v 40c 1.0v +25c 1.0v +85c 1.0v +125c 1.0v typical device 0.25 0.00 0.25 0.50 0.75 1.00 inl (lsb) 1.00 0.75 0.50 0 8 16 24 32 40 48 56 64 dac wiper code 40c 2.0v +25c 2.0v +85c 2.0v +125c 2.0v 40c 1.8v +25c 1.8v +85c 1.8v +125c 1.8v 40c 1.0v +25c 1.0v +85c 1.0v +125c 1.0v typical device analog performance specified for vdd 2.7v. 0.25 0.00 0.25 0.50 0.75 1.00 inl (lsb) 1.00 0.75 0.50 0 8 16 24 32 40 48 56 64 dac wiper code 40c 1.6v +25c 1.6v +85c 1.6v +125c 1.6v 40c 1.0v +25c 1.0v +85c 1.0v +125c 1.0v typical device analog performance specified for vdd 2.7v.
mcp47a1 ds25154a-page 12 ? 2012 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = v ref = 5v, v ss = 0v, r l = 5 k ? , c l = 1 nf. figure 2-5: dnl vs. code (00h to 3fh) and temperature. v dd = 5.5v, v ref = 5.5v, 2.7v, 1.8v, and 1.0v. figure 2-6: dnl vs. code (00h to 3fh) and temperature. v dd = 2.7v, v ref = 2.7v, 1.8v, and 1.0v. figure 2-7: dnl vs. code (00h to 3fh) and temperature. v dd = 2.0v, v ref = 2.0v, 1.8v, and 1.0v. figure 2-8: dnl vs. code (00h to 3fh) and temperature. v dd = 1.8v, v ref = 1.6v, and 1.0v. 0.00 0.25 0.50 dnl (lsb) 40c 5.5v +25c 5.5v +85c 5.5v +125c 5.5v 40c 2.7v +25c 2.7v +85c 2.7v +125c 2.7v 40c 1.8v +25c 1.8v +85c 1.8v +125c 1.8v 40c 1.0v +25c 1.0v +85c 1.0v +125c 1.0v 0.50 0.25 0 8 16 24 32 40 48 56 64 dac wiper code typical device 0.00 0.25 0.50 dnl (lsb) 40c 2.7v +25c 2.7v +85c 2.7v +125c 2.7v 40c 1.8v +25c 1.8v +85c 1.8v +125c 1.8v 40c 1.0v +25c 1.0v +85c 1.0v +125c 1.0v 0.50 0.25 0 8 16 24 32 40 48 56 64 dac wiper code typical device 0.00 0.25 0.50 dnl (lsb) 40c 2.0v +25c 2.0v +85c 2.0v +125c 2.0v 40c 1.8v +25c 1.8v +85c 1.8v +125c 1.8v 40c 1.0v +25c 1.0v +85c 1.0v +125c 1.0v 0.50 0.25 0 8 16 24 32 40 48 56 64 dac wiper code typical device analog performance specified for vdd 2.7v. 0.00 0.25 0.50 dnl (lsb) 40c 1.6v +25c 1.6v +85c 1.6v +125c 1.6v 40c 1.0v +25c 1.0v +85c 1.0v +125c 1.0v 0.50 0.25 0 8 16 24 32 40 48 56 64 dac wiper code typical device analog performance specified for vdd 2.7v.
? 2012 microchip technology inc. ds25154a-page 13 mcp47a1 note: unless otherwise indicated, t a = +25c, v dd = v ref = 5v, v ss = 0v, r l = 5 k ? , c l = 1 nf. figure 2-9: full scale error (fse) vs. temperature. v dd = 5.5v, v ref = 5.5v, 2.7v, 1.8v, and 1.0v. figure 2-10: full scale error (fse) vs. temperature. v dd = 2.7v, v ref = 2.7v, 1.8v, and 1.0v. figure 2-11: full scale error (fse) vs. temperature. v dd = 2.0v, v ref = 2.0v, 1.8v, and 1.0v. figure 2-12: full scale error (fse) vs. temperature. v dd = 1.8v, v ref = 1.6v, and 1.0v. 0.60 0.40 0.20 0.00 l scale error (lsb) when v =v 1.00 0.80 40 20 0 20 40 60 80 100 120 ful l temperature (c) fse 5.5v fse 2.7v fse 1.8v fse 1.0v when v ref = v dd typical device 0.60 0.40 0.20 0.00 l scale error (lsb) 1.00 0.80 40 20 0 20 40 60 80 100 120 ful l temperature (c) fse 2.7v fse 1.8v fse 1.0v whenv ref =v dd typical device 1.00 0.80 0.60 0.40 0.20 0.00 l scale error (lsb) 1.60 1.40 1.20 40 20 0 20 40 60 80 100 120 ful l temperature (c) fse 2.0v fse 1.8v fse 1.0v typical device analog performance specified for vdd 2.7v. 3.00 2.00 1.00 0.00 l scale error (lsb) 5.00 4.00 40 20 0 20 40 60 80 100 120 ful l temperature (c) fse 1.6v fse 1.0v typical device analog performance specified for vdd 2.7v.
mcp47a1 ds25154a-page 14 ? 2012 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = v ref = 5v, v ss = 0v, r l = 5 k ? , c l = 1 nf. figure 2-13: zero scale error (zse) vs. temperature. v dd = 5.5v, v ref = 5.5v, 2.7v, 1.8v, and 1.0v. figure 2-14: zero scale error (zse) vs. temperature. v dd = 2.7v, v ref = 2.7v, 1.8v, and 1.0v. figure 2-15: zero scale error (zse) vs. temperature. v dd = 2.0v, v ref = 2.0v, 1.8v, and 1.0v. figure 2-16: zero scale error (zse) vs. temperature. v dd = 1.8v, v ref = 1.6v, and 1.0v. 0.40 0.60 0.80 1.00 o scale error (lsb) zse 5.5v zse 2.7v zse 1.8v zse 1.0v 0.00 0.20 4020 0 20406080100120 zer o temperature (c) typical device 0.40 0.60 0.80 1.00 o scale error (lsb) zse 2.7v zse 1.8v zse 1.0v 0.00 0.20 4020 0 20406080100120 zer o temperature (c) typical device 0.40 0.60 0.80 1.00 o scale error (lsb) zse 2.0v zse 1.8v zse 1.0v 0.00 0.20 4020 0 20406080100120 zer o temperature (c) typical device analog performance specified for vdd 2.7v. 0.40 0.60 0.80 1.00 o scale error (lsb) zse 1.6v zse 1.0v 0.00 0.20 4020 0 20406080100120 zer o temperature (c) typical device analog performance specified for vdd 2.7v.
? 2012 microchip technology inc. ds25154a-page 15 mcp47a1 note: unless otherwise indicated, t a = +25c, v dd = v ref = 5v, v ss = 0v, r l = 5 k ? , c l = 1 nf. figure 2-17: total unadjusted error vs. code and temperature. v dd = 5.5v, v ref = 5.5v, 2.7v, 1.8v, and 1.0v. figure 2-18: total unadjusted error vs. code and temperature. v dd = 2.7v, v ref = 2.7v, 1.8v, and 1.0v. figure 2-19: total unadjusted error vs. code and temperature. v dd = 2.0v, v ref = 2.0v, 1.8v, and 1.0v. figure 2-20: total unadjusted error vs. code and temperature. v dd = 1.8v, v ref = 1.6v, and 1.0v. 0.00 0.25 0.50 0.75 1.00 s ted error (lsb) 40c 5.5v +25c 5.5v +85c 5.5v +125c 5.5v 40c 2.7v +25c 2.7v +85c 2.7v +125c 2.7v 40c 1.8v +25c 1.8v +85c 1.8v +125c 1.8v 40c 1.0v +25c 1.0v +85c 1.0v +125c 1.0v 1.00 0.75 0.50 0.25 0 8 16 24 32 40 48 56 64 total unadju s dac wiper code whenv ref =v dd (code=64) typical device 0.25 0.00 0.25 0.50 0.75 1.00 u nadjusted error (lsb) 40c 2.7v +25c 2.7v +85c 2.7v +125c 2.7v 40c 1.8v +25c 1.8v +85c 1.8v +125c 1.8v 40c 1.0v +25c 1.0v +85c 1.0v +125c 1.0v 1.00 0.75 0.50 0 8 16 24 32 40 48 56 64 total u dac wiper code whenv ref =v dd (code=64) typical device 0.50 0.25 0.00 0.25 0.50 0.75 1.00 u nadjusted error (lsb) 40c 2.0v +25c 2.0v +85c 2.0v +125c 2.0v 40c 1.8v +25c 1.8v +85c 1.8v +125c 1.8v 40c 1.0v +25c 1.0v +85c 1.0v +125c 1.0v 1.50 1.25 1.00 0.75 0 8 16 24 32 40 48 56 64 total u dac wiper code typical device analog performance specified for vdd 2.7v. 3.00 2.00 1.00 0.00 1.00 u nadjusted error (lsb) 40c 1.6v +25c 1.6v +85c 1.6v +125c 1.6v 40c 1.0v +25c 1.0v +85c 1.0v +125c 1.0v whenv ref =1.6v (duetooutputdriverlinearityatv dd =1.8v) 5.00 4.00 0 8 16 24 32 40 48 56 64 total u dac wiper code typical device analog performance specified for vdd 2.7v.
mcp47a1 ds25154a-page 16 ? 2012 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = v ref = 5v, v ss = 0v, r l = 5 k ? , c l = 1 nf. figure 2-21: v out tempco vs. code ( ( ( ( v out(+125c) - v out(-40c) ) / v out(+25c,code=fs) ) / 165 ) * 1,000,000 ), v dd = 5.5v, v ref = 5.5v, 2.7v, 1.8v, and 1.0v. figure 2-22: v out tempco vs. code ( ( ( ( v out(+125c) - v out(-40c) ) / v out(+25c,code=fs) ) / 165 ) * 1,000,000 ), v dd = 2.7v, v ref = 2.7v, 1.8v, and 1.0v. figure 2-23: v out tempco vs. code ( ( ( ( v out(+125c) - v out(-40c) ) / v out(+25c,code=fs) ) / 165 ) * 1,000,000 ), v dd = 2.0v, v ref = 2.0v, 1.8v, and 1.0v. figure 2-24: v out tempco vs. code ( ( ( ( v out(+125c) - v out(-40c) ) / v out(+25c,code=fs) ) / 165 ) * 1,000,000 ), v dd = 1.8v, v ref = 1.6v, and 1.0v. 000 2.00 4.00 6.00 8.00 10.00 p er c ppm/c 5.5v ppm/c2.7v ppm/c 1.8v ppm/c 1.0v 10.00 8.00 6.00 4.00 2.00 0 . 00 0 8 16 24 32 40 48 56 64 ppm p dac wiper code typical device 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 ppm per c ppm/c 2.7v ppm/c 1.8v ppm/c 1.0v 10.00 8.00 6.00 4.00 2.00 0 8 16 24 32 40 48 56 64 dac wiper code typical device 25.00 30.00 35.00 40.00 45.00 50.00 55.00 60.00 65.00 70.00 75.00 80.00 85.00 ppm per c ppm/c 2.0v ppm/c 1.8v ppm/c 1.0v 10.00 5.00 0.00 5.00 10.00 15.00 20.00 0 8 16 24 32 40 48 56 64 dac wiper code typical device analog performance specified for vdd 2.7v. 110 130 150 170 190 210 230 250 270 290 310 330 350 ppm per c ppm/c 1.8v ppm/c 1.0v 10 10 30 50 70 90 110 0 8 16 24 32 40 48 56 64 dac wiper code typical device analog performance specified for vdd 2.7v.
? 2012 microchip technology inc. ds25154a-page 17 mcp47a1 note: unless otherwise indicated, t a = +25c, v dd = v ref = 5v, v ss = 0v, r l = 5 k ? , c l = 1 nf. figure 2-25: v ih / v il threshold of sda/scl inputs vs. temperature and v dd . figure 2-26: v ol (sda) vs. v dd and temperature. figure 2-27: interface active current (i dd ) vs. scl frequency (f scl ) and temperature v dd = 1.8v, 2.7v and 5.5v, v ref = 1.0v and v dd . (no load on v out ). figure 2-28: interface inactive current (static) vs. temperature and v dd . v dd = 1.8v, 2.7v and 5.5v, v ref = 1.0v and v dd . (no load on v out , scl = sda = v dd ). 0.4 0.6 0.8 1.0 o ltage / v dd vil 5.5v vil 2.7v vil 1.8v vih 5.5v vih 2.7v vih 1.8v 0.0 0.2 -40-20 0 20406080100120 v o temperature (c) typical device 0.2 0.3 0.4 0.5 v oltage (v) vol 5.5v vol 2.7v vol 1.8v 0.0 0.1 -40-20 0 20406080100120 v temperature (c) typical device 100 120 140 160 180 200 220 u rrent (ua) 400khz 5.5v 400khz 3.3v 400khz 2.7v 400khz 1.8v 100khz 5.5v 100khz 3.3v 100khz 2.7v 100khz 1.8v 40 60 80 -40-20 0 20406080100120 c u temperature (c) typical device 100 120 140 160 180 200 220 u rrent (ua) static 5.5v static 3.3v static 2.7v static 1.8v 40 60 80 -40-20 0 20406080100120 c u temperature (c) typical device
mcp47a1 ds25154a-page 18 ? 2012 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = v ref = 5v, v ss = 0v, r l = 5 k ? , c l = 1 nf. figure 2-29: v out vs. resistive load. v dd = 5.0v. figure 2-30: v out vs. resistive load. v dd = 2.7v. figure 2-31: v out vs. source / sink current. v dd = 5.0v. figure 2-32: v out vs. source / sink current. v dd = 2.7v. 2 3 4 5 v out (v) code = 40h 0 1 0 10002000300040005000 i source/sink (ma) typical device 0.9 1.8 2.7 v out (v) code = 40h 0.0 0 10002000300040005000 i source/sink (ma) typical device 2 3 4 5 v out (v) code = 00h code = 40h 0 1 02468101214 i source/sink (ma) typical device 0.9 1.8 2.7 v out (v) code = 00h code = 40h 0.0 0 2 4 6 8 10 12 14 i source/sink (ma) typical device
? 2012 microchip technology inc. ds25154a-page 19 mcp47a1 note: unless otherwise indicated, t a = +25c, v dd = v ref = 5v, v ss = 0v, r l = 5 k ? , c l = 1 nf. figure 2-33: v out accuracy vs. v dd and temperature. figure 2-34: r vref resistances vs. v dd and temperature. figure 2-35: -3db bandwidth vs frequency, v dd = 5.5v. 0.74 0.75 0.76 0.77 0.78 v out (v) vout 5.5v vout 2.7v 0.72 0.73 -40-20 0 20406080100120 temperature (c) typical device 19000 20000 21000 22000 23000 u rrent (ua) rvref5.5v rvref 2.7v rvref 1.8v 17000 18000 -40-20 0 20406080100120 c u temperature (c) typical device analog performance specified for vdd 2.7v. 18.00 15.00 12.00 9.00 6.00 3.00 0.00 3.00 db 30.00 27.00 24.00 21.00 1 10 100 1000 frequency (khz) fullscale vref=2.7v fullscalevref=5.5v midscalevref=2.7v midscalevref=5.5v quarterscalevref=2.7v quarterscalevref=5.5v typical device
mcp47a1 ds25154a-page 20 ? 2012 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = v ref = 5v, v ss = 0v, r l = 5 k ? , c l = 1 nf. figure 2-36: zero-scale to full-scale settling time (00h to 40h), v dd = 5.0v, v ref = 5.0v, r l = 5k ? , c l = 200 pf (time scale = 2 s / div). figure 2-37: full-scale to zero-scale settling time (40h to 00h), v dd = 5.0v, v ref = 5.0v, r l = 5k ? , c l = 200 pf (time scale = 2 s / div). figure 2-38: half-scale settling time (10h to 30h), v dd = 5.0v, v ref = 5.0v, r l = 5k ? , c l = 200 pf. (time scale = 2 s / div) figure 2-39: half-scale settling time (30h to 10h), v dd = 5.0v, v ref = 5.0v, r l = 5k ? , c l = 200 pf (time scale = 2 s / div).
? 2012 microchip technology inc. ds25154a-page 21 mcp47a1 note: unless otherwise indicated, t a = +25c, v dd = v ref = 5v, v ss = 0v, r l = 5 k ? , c l = 1 nf. figure 2-40: digital feedthrough (scl signal coupling to v out pin); v dd = 5.0v, v ref = 5.0v, f scl = 100 khz, v out = 20h (v out voltage scale = 20 mv/div, time scale = 2 s / div). 2.1 test circuit figure 2-41: -3 db gain vs. frequency test. + - v out 1.0v dc v ref w v in 4.0v (peak to peak) v dd
mcp47a1 ds25154a-page 22 ? 2012 microchip technology inc. notes:
? 2012 microchip technology inc. ds25154a-page 23 mcp47a1 3.0 pin descriptions the descriptions of the pins are listed in table 3-1 . additional descriptions of the device pins follow. table 3-1: pinout description for the mcp47a1 3.1 positive power supply input (v dd ) the v dd pin is the device?s positive power supply input. the input power supply is relative to v ss and can range from 1.8v to 5.5v. a decoupling capacitor on v dd (to v ss ) is recommended to achieve maximum performance. analog specifications are tested from 2.7v. 3.2 ground (v ss ) the v ss pin is the device ground reference. 3.3 i 2 c serial clock (scl) the scl pin is the serial clock pin of the i 2 c interface. the mcp47a1 acts only as a slave and the scl pin accepts only external serial clocks. the scl pin is an open-drain output. refer to section 5.0 ?serial interface - i 2 c module? for more details of i 2 c serial interface communication. 3.4 i 2 c serial data (sda) the sda pin is the serial data pin of the i 2 c interface. the sda pin has a schmitt trigger input and an open-drain output. refer to section 5.0 ?serial interface - i 2 c module? for more details of i 2 c serial interface communication. 3.5 analog output voltage pin (v out ) v out is the dac analog output pin. the dac output has an output amplifier. v out can swing from approximately v zs (= v ss ) to v fs (= v ref ). in normal mode, the dc impedance of the output pin is about 1 ? . see section 7.0 ?output buffer? for more information. 3.6 voltage reference pin (v ref ) this pin is the external voltage reference input. the v ref pin signal is unbuffered so the reference voltage must have the current capability not to drop its voltage when connected to the internal resistor ladder circuit (20 k ? typical). see section 6.0 ?resistor network? for more information. pin name package pin type buffer type function sc70-6 v dd 1 p ? positive power supply input v ss 2 p ? ground scl 3 i/o st (od) i 2 c serial clock pin sda 4 i/o st (od) i 2 c serial data pin v out 5 i/o a output voltage v ref 6 i/o a reference voltage for v out output legend: a = analog input st (od) = schmitt trigger with open drain i = input o = output i/o = input/output p = power
mcp47a1 ds25154a-page 24 ? 2012 microchip technology inc. notes:
? 2012 microchip technology inc. ds25154a-page 25 mcp47a1 4.0 general overview the mcp47a1 device is a general purpose dac intended to be used in applications where a program- mable voltage output with moderate bandwidth is desired. applications generally suited for the mcp47a1 devices include: ? set point or offset trimming ? sensor calibration ? cost-sensitive mechanical trim pot replacement the mcp47a1 has four main functional blocks. these are: ? por/bor operation ? serial interface - i 2 c module ? resistor network ? output buffer the por/bor operation is discussed in this section and the i 2 c and resistor network operation are described in their own sections. the commands are discussed in section 5.3, serial commands . figure 4-1 shows a block diagram for the resistive network of the device. an external pin, called v ref , is the dac?s reference voltage. the resistance from the v ref pin to ground is typically 20 k ? . the reference voltage connected to the v ref pin needs to support this resistive load. this resistor network functions as a windowed voltage divider. this means that the v out pin?s voltage range is from approximately v ss to approximately v ref . figure 4-1: resistor network and output buffer block diagram. r fs a r s r s r s b r w ( 1 ) w analog switch mux note 1: the wiper resistance is tap dependent. that is, each tap selection resistance has a small variation. r w ( 1 ) r w ( 1 ) r w ( 1 ) r zs 2: the r fs and r zs resistances are determined by the analog switches that connect the resistor network to the other circuitry. v ref r ab goes to output buffer?s input op amp - + v out
mcp47a1 ds25154a-page 26 ? 2012 microchip technology inc. 4.1 por/bor operation the power-on reset is the case where the device has power applied to it from v ss . the brown-out reset occurs when a device had power applied to it, and that power (voltage) drops below the specified range. the device?s ram retention voltage (v ram ) is lower than the por/bor voltage trip point (v por /v bor ). this ensures that when the device power-on reset occurs, the logic can retain default values that are loaded. the maximum v por /v bor voltage is less than 1.8v. when v por /v bor < v dd < 1.8v, the dacs? elec- trical performance may not meet the data sheet specifications. table 4-2 shows the dac?s level of functionality across the entire v dd range, while figure 4-2 illustrates the power-up and brown-out functionality. 4.1.1 power-on reset when the device powers up, the device v dd will cross the v por /v bor voltage. once the v dd voltage crosses the v por /v bor voltage, the following happens: ? volatile serial shift register / wiper register is loaded with the default values (see table 4-1 ) ? the device is capable of digital operation table 4-1: default por wiper setting selection 4.1.2 brown-out reset when the device powers down, the device v dd will cross the v por /v bor voltage (v bor < 1.8v). once the v dd voltage decreases below the v por /v bor voltage, the following happens: ? serial interface is disabled if the v dd voltage decreases below the v ram voltage, the following happens: ? volatile serial shift register (ssr) and wiper register may become corrupted as the voltage recovers above the v por /v bor voltage, see section 4.1.1 ?power-on reset? . serial commands not completed due to a brown-out condition may cause the memory location to become corrupted. 4.1.3 wiper register (ram) the wiper register is 7-bit volatile memory that starts functioning at the ram retention voltage (v ram ). the wiper register will be loaded with the default wiper value when v dd rises above the v por /v bor voltage. 4.1.4 device currents the current of the device can be classified into two modes of the device operation. these are: ? serial interface inactive (static operation) ? serial interface active static operation occurs when a stop condition is received. static operation is exited when a start condition is received. table 4-2: device functionality at each v dd region ( note 1 ) note: at voltages below v dd(min) , the electrical performance of the i 2 c interface may not meet the data sheet specifications default por wiper setting serial shift register (ssr) wiper register mid-scale 20h 20h v dd level serial interface v out dac register setting comment v dd < v th ignored ?unknown? unknown v th < v dd < v bor ignored pulled low unknown v bor ? v dd < 1.8v ?unknown? operational with reduced electrical specifications dac register loaded with por/bor value 1.8v ? v dd ? 5.5v accepted operational dac register determines serial value meets the data sheet specifications note 1: for system voltages below the minimum operating voltage, it is recommended to use a voltage supervisor to hold the system in reset. this will ensure that mcp47x1 commands are not attempted out of the oper- ating range of the device.
? 2012 microchip technology inc. ds25154a-page 27 mcp47a1 figure 4-2: power-up and brown-out. v por/bor v ss v dd outside specified normal operation range device?s serial wiper forced to default por/bor setting v bor delay normal operation range 1.8v interface is ?not operational? ac/dc range below minimum operating voltage v ram
mcp47a1 ds25154a-page 28 ? 2012 microchip technology inc. notes:
? 2012 microchip technology inc. ds25154a-page 29 mcp47a1 5.0 serial interface - i 2 c module a 2-wire i 2 c serial protocol is used to write or read the dac?s wiper register. the i 2 c protocol utilizes the scl input pin and sda input/output pin. the i 2 c serial interface supports the following features: ? slave mode of operation ? 7-bit addressing ? the following clock rate modes are supported: - standard mode, bit rates up to 100 kb/s - fast mode, bit rates up to 400 kb/s ? support multi-master applications the serial clock is generated by the master. the i 2 c module is compatible with the nxp i 2 c specification (# um10204). only the field types, field lengths, timings, etc. of a frame are defined. the frame content defines the behavior of the device. the frame content for the mcp47a1 device is defined in this sec- tion of the data sheet. figure 5-1 shows a typical i 2 c bus configuration. figure 5-1: typical application i 2 c bus configurations. refer to section 2.0 ?typical performance curves? , ac/dc electrical characteristics table for detailed input threshold and timing specifications. 5.1 i 2 c i/o considerations i 2 c specifications require active low, passive high functionality on devices interfacing to the bus. since devices may be operating on separate power supply sources, esd clamping diodes are not permitted. the specification recommends using open drain transistors tied to v ss (common) with a pull-up resistor. the specification makes some general recommendations on the size of this pull-up, but does not specify the exact value since bus speeds and bus capacitance impacts the pull-up value for optimum system performance. common pull-up values range from 1 k ? to a maximum of ~10 k ? . power sensitive applications tend to choose higher values to minimize current losses during communication but these applications also typically utilize lower v dd . the sda and scl float (are not driving) when the device is powered down. a "glitch" filter is on the scl and sda pins when the pin is an input. when these pins are an output, there is a slew rate control of the pin that is independent of device frequency. 5.1.1 slope control the device implements slope control on the sda output. the slope control is defined by the fast mode specifications. for fast (fs) mode, the device has spike suppression and schmidt trigger inputs on the sda and scl pins. single i 2 c bus configuration host controller device 1 device 3 device n device 2 device 4
mcp47a1 ds25154a-page 30 ? 2012 microchip technology inc. 5.2 i 2 c bit definitions i 2 c bit definitions include: ? start bit ? data bit ? acknowledge (a) bit ? repeated start bit ? stop bit ? clock stretching figure 5-8 shows the waveform for these states. 5.2.1 start bit the start bit (see figure 5-2 ) indicates the beginning of a data transfer sequence. the start bit is defined as the sda signal falling when the scl signal is ?high?. figure 5-2: start bit. 5.2.2 data bit the sda signal may change state while the scl signal is low. while the scl signal is high, the sda signal must be stable (see figure 5-3 ). figure 5-3: data bit. 5.2.3 acknowledge (a) bit the a bit (see figure 5-4 ) is a response from the slave device to the master device. depending on the context of the transfer sequence, the a bit may indicate different things. typically the slave device will supply an a response after the start bit and 8 ?data? bits have been received. the a bit will have the sda signal low. figure 5-4: acknowledge waveform. if the slave address is not valid, the slave device will issue a not a (a ). the a bit will have the sda signal high. if an error condition occurs (such as an a instead of a) then a start bit must be issued to reset the command state machine. table 5-1: mcp47a1 a / a responses 5.2.4 repeated start bit the repeated start bit (see figure 5-5 ) indicates the current master device wishes to continue communicating with the current slave device without releasing the i 2 c bus. the repeated start condition is the same as the start condition, except that the repeated start bit follows a start bit (with the data bits + a bit) and not a stop bit. the start bit is the beginning of a data transfer sequence and is defined as the sda signal falling when the scl signal is ?high?. figure 5-5: repeat start condition waveform. sda scl s 1st bit 2nd bit sda scl 1st bit 2nd bit a 8 d0 9 sda scl event acknowledge bit response comment general call a slave address valid a slave address not valid a bus collision n.a. i 2 c module resets, or a ?don?t care? if the collision occurs on the masters ?start bit?. note 1: a bus collision during the repeated start condition occurs if: ? sda is sampled low when scl goes from low to high. ? scl goes low before sda is asserted low. this may indicate that another master is attempting to transmit a data " 1 ". sda scl sr = repeated start 1st bit
? 2012 microchip technology inc. ds25154a-page 31 mcp47a1 5.2.5 stop bit the stop bit (see figure 5-6 ) indicates the end of the i 2 c data transfer sequence. the stop bit is defined as the sda signal rising when the scl signal is ?high?. a stop bit resets the i 2 c interface of the other devices. figure 5-6: stop condition receive or transmit mode. 5.2.6 clock stretching ?clock stretching? is something that the secondary device can do, to allow additional time to ?respond? to the ?data? that has been received. the mcp47a1 will not stretch the clock signal (scl) since memory read accesses occur fast enough. 5.2.7 aborting a transmission if any part of the i 2 c transmission does not meet the command format, it is aborted. this can be intentionally accomplished with a start or stop condition. this is done so that noisy transmissions (usually an extra start or stop condition) are aborted before they corrupt the device. 5.2.8 ignoring an i 2 c transmission and ?falling off? the bus the mcp47a1 expects to receive entire, valid i 2 c com- mands and will assume any command not defined as a valid command is due to a bus corruption, and will enter a passive high condition on the sda signal. all signals will be ignored until the next valid start condition and control byte are received. figure 5-7: typical 16-bit i 2 c waveform format. figure 5-8: i 2 c data states and bit sequence. scl sda a / a p 1st sda scl s 2nd 3rd 4th 5th 6th 7th 8th p a/a bit bit bit bit bit bit bit bit 1st 2nd 3rd 4th 5th 6th 7th 8th a/a bit bit bit bit bit bit bit bit scl sda start condition stop condition data allowed to change data or a valid
mcp47a1 ds25154a-page 32 ? 2012 microchip technology inc. 5.2.9 i 2 c command protocol the mcp47a1 is a slave i 2 c device which supports 7- bit slave addressing. the slave address contains seven fixed bits. figure 5-9 shows the control byte format. 5.2.9.1 control byte (slave address) the control byte is always preceded by a start condition. the control byte contains the slave address consisting of seven fixed bits and the r/w bit. figure 5- 9 shows the control byte format and tab l e 5 - 2 shows the i 2 c address for the devices. figure 5-9: slave address bits in the i 2 c control byte. table 5-2: device i 2 c address 5.2.9.2 hardware address pins the mcp47a1 does not support hardware address bits. 5.2.10 general call the general call is a method that the master device can communicate with all other slave devices. the mcp47a1 devices do not respond to general call address and commands, and therefore the communications are not acknowledged. figure 5-10: general call formats. sa6a5a4a3a2a1a0r/w a/a start bit slave address r/w bit a bit (controlled by slave device) r/w = 0 = write r/w = 1 = read a = 0 = slave device acknowledges byte a = 1 = slave device does not acknowledge byte ?0? ?1? ?0? ?1? ?1? ?1? ?0? device i 2 c address binary hex (1) code comment mcp47a1 ? 0101110 ?0x5c a0 ? 0111110 ?0x7c a1 note 1: the lsb of the 8-bit hex code is the i 2 c read/write (r/w) bit. this hex value has a r/w bit = ?0? (write). if the r/w bit reflected a read, these values would be 0x5d and 0x7d. note 1: the mcp47a1 device supports two differ- ent i 2 c address (a0 and a1). this allows two mcp47a1 devices on the same i 2 c bus. 0 000 s 0000 x xxxx axx 0 ap general call address second byte ?7-bit command? reserved 7-bit commands (by i 2 c specification - nxp specification # um10204, ver. 03 16 january 2007) ?0000 011?b - reset and write programmable part of slave address by hardware ?0000 010?b - write programmable part of slave address by hardware ?0000 000?b - not allowed the following is a ?hardware general call? format 0 000 s 0000 x xxxx a xx1a general call address second byte ?7-bit command? x xxxx xxxap n occurrences of (data + a / a) this indicates a ?hardware general call?. mcp47a1 will ignore this byte and all following bytes (and a), until a stop bit (p) is encountered.
? 2012 microchip technology inc. ds25154a-page 33 mcp47a1 5.3 serial commands the mcp47a1 devices support two serial commands. these commands are: ? write operation ? read operations the i 2 c command formats have been defined to support the smbus version 2.0 write byte/word protocol formats and read byte/word protocol formats. the smbus specification that defines this operation is section 5 of the version 2.0 document (august 3, 2000). this protocol format may be convenient for customers using library routines for the i 2 c bus, where all they need to do is specify the command (read, write, ...) with the device address, the register address, and the data. 5.3.1 write operation the write operation requires the start condition, control byte, acknowledge, command code, acknowledge, data byte, acknowledge and stop (or restart) condition. the control (slave address) byte requires the r/w bit equal to a logic zero (r/w = ?0? ) to generate a write sequence. the mcp47a1 is responsible for generating the acknowledge (a) bits. data is written to the mcp47a1 after every byte transfer (during the a bit). if a stop or restart condition is generated during a data transfer (before the a bit), the data will not be written to mcp47a1. data bytes may be written after each acknowledge. the command is terminated once a stop (p) condition occurs. refer to figure 5-11 for the single byte write sequence and figure 5-12 for the generic (multi-byte) write sequence. for a single byte write, the master sends a stop or restart condition after the 1st data byte is sent. the msb of each data byte is a don?t care, since the wiper register is only 7-bits wide. the command is terminated once a stop (p) or restart (s) condition occurs. figure 5-13 shows the i 2 c write communication behavior of the master device and the mcp47a1 device and the resultant i 2 c bus values. 5.3.2 read operations the read operation requires the start condition, control byte, acknowledge, command code, acknowledge, restart condition, control byte, acknowledge, data byte, the master generating the a and stop (or restart) condition. the first control byte requires the r/w bit equal to a logic zero (r/w = ?0? ) to write the command code, while the second control byte requires the r/w bit equal to a logic one (r/w = ?1? ) to generate a read sequence. the mcp47a1 will a the slave address byte and a all the data bytes. the i 2 c master will a the slave address byte and the last data byte. if there are multiple data bytes, the i 2 c master will a all data bytes except the last data byte (which it will a ). the mcp47a1 maintains control of the sda signal until all data bits have been clocked out. the command is terminated once a stop (p) or restart (s) condition occurs. refer to figure 5-14 for the read command sequence. for a single read, the master sends a stop or restart condition after the 1st data byte (and a bit) is sent from the slave. the msb of each data byte is always a ? 0 ?, since the wiper register is only 7-bits wide. figure 5-15 shows the i 2 c read communication behavior of the master device and the mcp47a1 device and the resultant i 2 c bus values. note: a command code with a non-zero value will cause the data not to be written to the wiper register note: a command code with a non-zero value will cause the data not to be read from the wiper register
mcp47a1 ds25154a-page 34 ? 2012 microchip technology inc. figure 5-11: i 2 c single byte write command format. figure 5-12: i 2 c write command format. stop bit slave address byte (1) command code data byte 1 010 s 1100 0 a000ad3 x d6d5d4 d2d1d0 a fixed address p read/write bit ( ?0? = write) 00 00 s = start condition p = stop condition a = acknowledge x = don?t care r/w = read/write bit d6:d0 = data bits legend note 1: example using slave address option a0 (5ch). stop bit slave address byte (1) command code data byte 1 010 s 111 0 0 a000ad3 x d6d5d4 d2d1d0 a fixed address data byte data byte ad3 x d6d5d4 d2d1d0 a p read/write bit ( ?0? = write) 00 00 d3 d2 d1 d0 xd6d5d4 s = start condition p = stop condition a = acknowledge x = don?t care r/w = read/write bit d6:d0 = data bits legend note 1: example using slave address option a0 (5ch).
? 2012 microchip technology inc. ds25154a-page 35 mcp47a1 figure 5-13: i 2 c write communication behavior. write 1 byte with command code = 00h write 2 byte with command code = 00h s slave address r / w a c k command code a c k data byte a c kp master s0101110010000000010ddddddd1p mcp47a1 0 0 0 i 2 c bus s0101110000000000000ddddddd0p s slave address r / w a c k command code a c k data byte a c k master s0101110010000000010ddddddd1 mcp47a1 0 0 0 i 2 c bus s0101110000000000000ddddddd0 data byte a c kp master 0ddddddd1p mcp47a1 0 i 2 c bus 0ddddddd0p
mcp47a1 ds25154a-page 36 ? 2012 microchip technology inc. figure 5-14: i 2 c read command format. figure 5-15: i 2 c read communication behavior. stop bit slave address byte (3) command code 1 010 s1100 0 a000a slave address byte (3) data byte ad3 0 d6d5d4 d2d1d0a (2) p read/write bit ( ?0? = write) 00 00 11 01 01 01 s = start condition p = stop condition a = acknowledge x = don?t care r/w = read/write bit d6:d0 = data bits legend s read/write bit ( ?1? = read) note 1: master device is responsible for ack / nack signal. if a nack signal occurs, the mcp47a1 will abort this transfer and release the bus. 2: the master device will not ack , and the mcp47a1 will release the bus so the master device can generate a stop or repeated start condition. 3: example using slave address option a0 (5ch). read 1 byte with command code = 00h read 2 byte with command code = 00h sslave address r / w a c k command code a c k r sslave address r / w a c k master s010111001000000001s010111011 mcp47a1 0 0 0 i 2 c bus s010111000000000000s010111010 data byte a c kp master 1 p mcp47a1 0ddddddd1 i 2 c bus 0ddddddd1p sslave address r / w a c k command code a c k r sslave address r / w a c k master s010111001000000001s010111011 mcp47a1 0 0 0 i 2 c bus s010111000000000000s010111010 data byte a c kdata byte a c kp master 0 1 p mcp47a1 0ddddddd10ddddddd1 i 2 c bus 0ddddddd00ddddddd1p
? 2012 microchip technology inc. ds25154a-page 37 mcp47a1 6.0 resistor network the resistor network is made up of an r ab resistor ladder. the r ab resistor has a typical resistance of 20 k ? . figure 6-1 shows a block diagram for the resistor network and output buffer. the resistance from the v ref pin to ground is referred to as r vref . the 7-bit i 2 c data byte (00h - 7fh) is decoded to the 6- bit wiper value (00h - 40h). section 6.3 describes the serial shift buffer to wiper register decoding. 6.1 r vref resistance r vref resistance is the resistance from the v ref pin to ground and is the r ab resistances. equation 6-1 shows how to calculate r vref . 6.1.1 v ref pin current (i vref ) the current into the v ref pin is dependent on the volt- age on the v ref pin (v ref ) and the r vref resistance. the v ref pin?s voltage source current capability should support a resistive load that is the minimum r vref resistance. equation 6-1: calculating r vref 6.2 r ab resistor ladder the r ab resistor ladder is a digital potentiometer in a voltage divider configuration. the r ab resistor ladder has 64 r s resistors in series. this resistor ladder has 65 wiper taps which allow wiper connectivity to the bottom (terminal b), zero-scale, and the top (terminal a), full-scale, of the resistor ladder (see figure 6-1 ). with an even number of r s resistors in the r ab ladder, when the wiper is at the mid-scale value, v out equals v ref / 2. the r ab resistance also includes the r fs and r zs resistances (see section 6.2.2 ). the r ab (and r s ) resistance has small variations over voltage and temperature. the typical r ab resistance is 10k ? . 6.2.1 the wiper the value in the volatile wiper register selects which analog switch to close, connecting the w terminal to the selected node of the resistor ladder. the wiper reg- ister value is derived from the serial shift register value (see section 6.3 ). any variation of the wiper resistance does not effect the voltage at the w terminal, and therefore the input of the output buffer. 6.2.2 r fs and r zs resistors the r fs and r zs resistances are artifacts of the r ab resistor implementation. these resistors are included in the block diagram to help better model the actual device operation. equation 6-2 shows how to estimate the r s , r fs , and r zs resistances, based on the measured voltages of v ref , v fs , and v zs and the measured current i vref . equation 6-2: estimating r s , r fs , and r zs r vref = (v ref ) (i vref ) v ref is the voltage on the v ref pin. i vref is the current into the v ref pin. v fs is the v out voltage when the wiper code is at full-scale. v zs is the v out voltage when the wiper code is at zero-scale. r fs = v ref i vref r zs = v zs i vref v s = ( v fs - v zs ) 64 where: r s = v s i vref
mcp47a1 ds25154a-page 38 ? 2012 microchip technology inc. figure 6-1: resistor network and output buffer block diagram. r s a r s r s r s b n = 64 n = 63 n = 62 n = 1 n = 0 r w (1) w analog mux note 1: the wiper resistance is tap dependent. that is, each tap selection resistance has a r w (1) r w (1) r w (1) r w (1) r ab / r vref r zs r fs v ref 64 * r s small variation. op amp - + v out wiper value output buffer ( section 7.0 ) resistor network ( section 6.0 ) (00h) (01h) (3eh) (3fh) (40h)
? 2012 microchip technology inc. ds25154a-page 39 mcp47a1 6.3 serial buffer to wiper register decode the i 2 c?s data byte is 8-bits, where only the lower 7- bits are implemented. this register is called the serial shift register (ssr). the wiper register supports addressing of 65 taps (6-bit resolution). table 6-1 shows the decoding of the serial shift register to the wiper register value. table 6-1: serial shift register value to wiper value 6.4 resistor variations (voltage and temperature) the r ab resistors are implemented to have minimal variations (by design). any variations should occur uniformly on all the resistor elements, so the resistor?s elements will track each other over temperature and process variations. the variation of the resistive elements over the operat- ing voltage range is also minimal. therefore the v ref resistance (r vref ) of the device has minimal variation due to operating voltage. since the v out pin?s voltage is ratiometric, and the resistive elements change uniformly over temperature, process, and operating voltage variations. minimal variation should be seen on the v out pin?s voltage. 6.5 por value a por/bor event will load the volatile serial shift register (and therefore wiper register) with the default value. ta b l e 6 - 2 shows the default values offered. table 6-2: por/bor settings note 1: the i 2 c write and read commands access the value in the serial shift regis- ter (ssr). 2: the msb of the i 2 c data byte is ignored and not loaded into the ssr. a write of c0h, will result in the same v out voltage as a write of 40h (mid-scale). a subse- quent read command (of the ssr) will result in a value of 40h. 3: the 7-bit ssr value is decoded to a 6-bit (65 taps) value that controls the wiper?s position. i 2 c write data ssr ( 1 ) wiper value ( 2 ) comment 00h 00h 00h wiper register at zero scale, v out = v ss 01h or 81h 01h 01h 02h or 82h 02h 02h ::: 20h or a0h 20h 20h mid-scale (por value), v out = (1/2) * v ref ::: 3eh or beh 3eh 3eh wiper register = ssr - 20h 3fh or bfh 3fh 3fh wiper register = ssr - 20h 40h - 7fh or c0h - ffh 40h - 7fh 40h wiper register at full scale, v out = v ref note 1: the serial shift register (ssr) is 7-bits wide and holds the value written from the i 2 c write command. an i 2 c read com- mand will read the value in this register. 2: the wiper value is the value that controls the resistor ladder?s wiper position. device setting register value (1) ssr wiper mcp47a1 mid-scale 20h or a0h 20h note 1: custom por/bor wiper setting options are available; contact the local microchip sales office for additional information. custom options have nre and minimum volume requirements.
mcp47a1 ds25154a-page 40 ? 2012 microchip technology inc. notes:
? 2012 microchip technology inc. ds25154a-page 41 mcp47a1 7.0 output buffer as the device powers up, the v out pin will float to an unknown value. when the device?s v dd is above the transistor threshold voltage of the device, the output will start being pulled low. after the v dd is above the por/bor trip point (v bor /v por ), the resistor net- work?s wiper will be loaded with the por value (20h, which is midscale). the output voltage of the buffer (v out ) may not be within specification until the device v dd is at 2.7v. the outputs? slew rate and settling time must also be taken into account. 7.1 output buffer / v out operation the dac output is buffered with a low power and precision output amplifier (op amp). this amplifier provides a rail-to-rail output with low offset voltage and low noise. the amplifier?s output can drive the resistive and capacitive loads without oscillation. the amplifier provides a maximum load current which is enough for most programmable voltage reference applications. figure 7-1 shows a block diagram. figure 7-1: output buffer block diagram. 7.1.1 output voltage the volatile dac register?s value controls the analog v out voltage. the volatile wiper register?s value is unsigned binary. the formula for the output voltage is given in equation 7-1 . equation 7-1: calculating output voltage (v out ) the serial shift register?s value will be latched on the falling edge of the acknowledge pulse of the write command?s last byte. then the v out voltage will start driving to the new value. the following events update the analog voltage output (v out ): ? power-on-reset. ? falling edge of the acknowledge pulse of the last write command byte. 7.1.2 step voltage (v s ) the step voltage is dependent on the device resolution (64 r s ) and the output voltage range (v zs to v fs ). equation 7-2 shows the calculation for the step resis- tance. equation 7-2: v s calculation table 7-1 shows the calculated v out voltages for the given volatile wiper register value. these calculations are based on different v ref voltage values (1.5v, 3.3v, and 5.0v) with an assumption that r fs = r zs = 0 ? . note 1: the load resistance must stay higher than 5k ? for the stable and expected analog output (to meet electrical specifications). refer to: ? section 1.0 ?electrical charac- teristics? for the specifications of the output amplifier. ? section 7.3 ?driving resistive and capacitive loads? for addi- tional design information. v out op amp gain =1x v w n = wiper code = 0 to 64; v out = v zs + (n * v s ) v zs is the v out voltage when the wiper code = 00h. v zs = 0v when r fs = r zs = 0 ? : v fs = v ref v s = (v fs - v zs ) 64 v fs is the v out voltage when the wiper code is at full-scale. v zs is the v out voltage when the wiper code is at zero-scale.
mcp47a1 ds25154a-page 42 ? 2012 microchip technology inc. table 7-1: theoretical dac output values wiper value v out ( 1 ) wiper value v out ( 1 ) ratio v ref ratio v ref hex dec 1.5 3.3 5.0 hex dec 1.5 3.3 5.0 00h 0 0.0000 0.0000 0.0000 0.0000 20h 32 0.5000 0.7500 1.6500 2.5000 01h 1 0.0156 0.0234 0.0516 0.0781 21h 33 0.5156 0.7734 1.7016 2.5781 02h 2 0.0313 0.0469 0.1031 0.1563 22h 34 0.5313 0.7969 1.7531 2.6563 03h 3 0.0469 0.0703 0.1547 0.2344 23h 35 0.5469 0.8203 1.8047 2.7344 04h 4 0.0625 0.0938 0.2063 0.3125 24h 36 0.5625 0.8438 1.8563 2.8125 05h 5 0.0781 0.1172 0.2578 0.3906 25h 37 0.5781 0.8672 1.9078 2.8906 06h 6 0.0938 0.1406 0.3094 0.4688 26h 38 0.5938 0.8906 1.9594 2.9688 07h 7 0.1094 0.1641 0.3609 0.5469 27h 39 0.6094 0.9141 2.0109 3.0469 08h 8 0.1250 0.1875 0.4125 0.6250 28h 40 0.6250 0.9375 2.0625 3.1250 09h 9 0.1406 0.2109 0.4641 0.7031 29h 41 0.6406 0.9609 2.1141 3.2031 0ah 10 0.1563 0.2344 0.5156 0.7813 2ah 42 0.6563 0.9844 2.1656 3.2813 0bh 11 0.1719 0.2578 0.5672 0.8594 2bh 43 0.6719 1.0078 2.2172 3.3594 0ch 12 0.1875 0.2813 0.6188 0.9375 2ch 44 0.6875 1.0313 2.2688 3.4375 0dh 13 0.2031 0.3047 0.6703 1.0156 2dh 45 0.7031 1.0547 2.3203 3.5156 0eh 14 0.2188 0.3281 0.7219 1.0938 2eh 46 0.7188 1.0781 2.3719 3.5938 0fh 15 0.2344 0.3516 0.7734 1.1719 2fh 47 0.7344 1.1016 2.4234 3.6719 10h 16 0.2500 0.3575 0.8250 1.2500 30h 48 0.7500 1.1250 2.4750 3.7500 11h 17 0.2656 0.3984 0.8766 1.3281 31h 49 0.7656 1.1484 2.5266 3.8281 12h 18 0.2813 0.4219 0.9281 1.4063 32h 50 0.7813 1.1719 2.5781 3.9063 13h 19 0.2969 0.4453 0.9797 1.4844 33h 51 0.7969 1.1953 2.6297 3.9844 14h 20 0.3125 0.4688 1.0313 1.5625 34h 52 0.8125 1.2188 2.6813 4.0625 15h 21 0.3281 0.4922 1.0828 1.6406 35h 53 0.8281 1.2422 2.7328 4.1406 16h 22 0.3438 0.5156 1.1344 1.7188 36h 54 0.8438 1.2656 2.7844 4.2188 17h 23 0.3594 0.5391 1.1859 1.7969 37h 55 0.8594 1.2891 2.8359 4.2969 18h 24 0.3750 0.5625 1.2375 1.8750 38h 56 0.8750 1.3125 2.8875 4.3750 19h 25 0.3906 0.5859 1.2891 1.9531 39h 57 0.8906 1.3359 2.9391 4.4531 1ah 26 0.4063 0.6094 1.3406 2.0313 3ah 58 0.9063 1.3594 2.9906 4.5313 1bh 27 0.4219 0.6328 1.3922 2.1094 3bh 59 0.9219 1.3828 3.0422 4.6094 1ch 28 0.4375 0.6563 1.4438 2.1875 3ch 60 0.9375 1.4063 3.0938 4.6875 1dh 29 0.4531 0.6797 1.4953 2.2656 3dh 61 0.9531 1.4297 3.1453 4.7656 1eh 30 0.4688 0.7031 1.5469 2.3438 3eh 62 0.9688 1.4531 3.1969 4.8438 1fh 31 0.4844 0.7266 1.5984 2.4219 3fh 63 0.9844 1.4766 3.2484 4.9219 40h 64 1.0000 1.5000 3.3000 5.0000 note 1: v out voltages based on r fs and r zs = 0 ? .
? 2012 microchip technology inc. ds25154a-page 43 mcp47a1 7.1.3 amplifier input voltage (v w ) to ensure that the amplifier is operating in its linear range, the voltage (v w ) into the output amplifier?s input has requirements that must be met. for device v dd voltages ? 2.7v, the amplifier is in the linear region for all v ref voltages ( ? 1.0v) and dac register codes. for device v dd voltages < 2.7v, there will be a voltage where the amplifier output is no longer linear with the amplifier input voltage (v w ). this is shown in figure 2- 20 , where v dd = 1.8v and the v ref = 1.6v. higher dac register codes are the first to encounter the nonlinearity of the output buffer. the nonlinearity is also influenced by the temperature of operation. figure 7-2 shows the trend of the amplifier linearity based on the device v dd / v ref voltages and the input voltage to the amplifier. the trend will also be affected by device temperature. v nl is the voltage where the amplifier?s output becomes nonlinear. while the v w voltage is less than the v nl voltage, the amplifier?s out- put is linear. once the device v dd has been lowered to where the amplifier?s nonlinear range increases, the two methods to keep v w < v nl are: 1. lower the v ref voltage 2. decrease the dac register code both methods reduce the maximum usable output voltage. figure 7-2: amplifier input (v w ) to amplifier output (v out ) general characteristics (v ref = v dd ). figure 7-3 shows the equations for solving for v out voltage, the v ref voltage, or the maximum dac register code, based on knowing the requirements for two of these variables. for v dd voltages below the specified analog performance voltage (2.7v), the calibration of the device could be done to ensure v out voltage is not driven into the output amplifier nonlinear region via the dac register value / v ref voltage. using the measured v nl voltage as the v out voltage will allow you to balance your selection of the v ref voltage and maximum dac code. the dac register code of 64 is the full-scale code. figure 7-3: solving for v out , v ref , or dac register code. ideal v out v w 0v dd / v ref v dd / actual v ref (based on device v dd = 1.8v v dd = 5.5v v dd and temperature) v out = v ref * dac code 64 v ref = 64 * v out dac code dac code = 64 * v out v ref
mcp47a1 ds25154a-page 44 ? 2012 microchip technology inc. 7.2 output slew rate figure 7-4 shows an example of the slew rate of the v out pin. the slew rate can be affected by the characteristics of the circuit connected to the v out pin. figure 7-4: v out pin slew rate. 7.2.1 small capacitive load with a small capacitive load, the output buffer?s current is not affected by the capacitive load (c l ). but still, the v out pin?s voltage is not a step transition from one output value (wiper code value) to the next output value. the change of the v out voltage is limited by the output buffer?s characteristics, so the v out pin voltage will have a slope from the old voltage to the new voltage. this slope is fixed for the output buffer, and is referred to as the buffer slew rate (sr buf ). 7.2.2 large capacitive load with a larger capacitive load, the slew rate is deter- mined by two factors: ? the output buffer?s short circuit current (i sc ) ?the v out pin?s external load i out cannot exceed the output buffer?s short circuit current (i sc ), which fixes the output buffer slew rate (sr buf ). the voltage on the capacitive load (c l ), v cl , changes at a rate proportional to i out , which fixes a capacitive load slew rate (sr cl ). so the v cl voltage slew rate is limited to the slower of the output buffer?s internally set slew rate (srbuf) and the capacitive load slew rate (sr cl ). 7.3 driving resistive and capacitive loads the v out pin can drive up to 100 pf of capacitive load in parallel with a 5 k ? resistive load (to meet electrical specifications). figure 2-29 shows the v out vs. resistive load. v out drops slowly as the load resistance decreases after about 3.5 k ? . it is recommended to use a load with r l greater than 5 k ? . driving large capacitive loads can cause stability problems for voltage feedback op amps. as the load capacitance increases, the feedback loop?s phase margin decreases and the closed-loop bandwidth is reduced. this produces gain peaking in the frequency response with overshoot and ringing in the step response. that is, since the v out pin?s voltage does not quickly follow the buffer?s input voltage (due to the large capacitive load), the output buffer will overshoot the desired target voltage. once the driver detects this overshoot, it compensates by forcing it to a voltage below the target. this causes voltage ringing on the v out pin. so, when driving large capacitive loads with the output buffer, a small series resistor (r iso ) at the output (see figure 7-5 ) improves the output buffer?s stability (feed- back loop?s phase margin) by making the output load resistive at higher frequencies. the bandwidth will be generally lower than the bandwidth with no capacitive load. figure 7-5: circuit to stabilize output buffer for large capacitive loads (c l ). the r iso resistor value for your circuit needs to be selected. the resulting frequency response peaking and step response overshoot for this r iso resistor value should be verified on the bench. modify the r iso ?s resistance value until the output characteristics meet your requirements. a method to evaluate the system?s performance is to inject a step voltage on the v ref pin and observe the v out pin?s characteristics. time slew rate = wiper = a v out v out(a) v out(b) wiper = b | v out(b) - v out(a) | ? t note: additional insight into circuit design for driving capacitive loads can be found in an884 ?driving capacitive loads with op amps? (ds00884). v out op amp v w c l r iso r l v cl
? 2012 microchip technology inc. ds25154a-page 45 mcp47a1 7.4 output errors the output error is caused by two factors. these are: ? characteristics of the resistor network ? characteristics of the output buffer figure 7-6 shows the components of the error on the output voltage. the first part of the error is from the resistor ladder and the r fs and r zs resistances. the second part is due to the output buffer?s input offset characteristics. the r fs and r zs resistances affect the voltage between v zs and v fs . the larger that r fs + r zs is, the smaller that the step voltage (v s ) will be (from the theoretical step voltage). the increase in the r fs and r zs resistances also effects the full scale error (fse), zero scale error (zse), and gain error. table 7-2 compares theoretical resistor network volt- ages for full scale and zero scale, where r fs = r zs = 0 ? , to an example where r fs and r zs and non-zero. the voltage calculations show cases of v ref = 5.0v and v ref = 1.5v. figure 2-34 shows r vref , r fs , and r zs resistances v dd . so, as the voltage reference (v ref ) decreases, the step voltages (v s ) decrease. at a low v ref voltage, the step voltage approaches the magnitude of the output buffer?s input offset voltage (design target of 4.5 mv). so, for low v ref voltages, the output buffer errors have greater influence on the v out voltage. table 7-2: calculation comparison figure 7-6: output voltage (v out ) error. example theoretical delta r vref 20,180 ? ? r fs 100 ? 0 ? 100 ? r zs 80 ? 0 ? 80 ? r 1 + 64*r s + r 2 30,000 ? 30,180 ? - 180 ? r 1 , r ab , r 2 10,000 ? 10,060 ? - 60 ? v ref 5.00 v ? v fs 3.3267 v 3.3333 v - 6.6 mv v zs 1.6700 v 1.6667 v + 3.3 mv v s 25.88 mv 26.04 mv - 0.16 mv v ref 1.5v ? v fs 0.9980 v 1.0000 v - 2.0 mv v zs 0.5010 v 0.5000 v + 1.0 mv v s 7.766 mv 7.813 mv - 0.047mv note 1: r vref = r 1 + r ab + r 2 , r ab = r fs + 64*r s + r zs . v s = (v fs - v zs ) / 64 v ref v ss ( r fs ? 0 ? ) ( r zs ? 0 ? ) theoretical v fs ( v ref ) theoretical v zs ( v ss ) v fs-rl v zs-rl variations due to output buffer?s input offset voltage and buffer?s impedance / load (due to r fs ? 0 ? ) v out(fs) v out(zs) (due to r zs ? 0 ? ) r ab = 64*r s step voltage (v s ) = * v ref (v fs - v zs ) 64 v s = v ref / 64 v ref v s 78.125mv 42.19mv 28.13mv 23.44mv 15.63mv 5.0v 2.7v 1.8v 1.5v 1.0v when r fs = r zs = 0 ? . when: r fs = r zs = 0 ? .
mcp47a1 ds25154a-page 46 ? 2012 microchip technology inc. notes:
? 2012 microchip technology inc. ds25154a-page 47 mcp47a1 8.0 applications examples the mcp47a1 family of devices are general purpose, single-channel voltage output dacs for various applications where a precision operation with low power is needed. the mcp47a1 devices are rail-to-rail output dacs designed to operate with a v dd range of 1.8v to 5.5v. the internal output op amplifier is robust enough to drive common, small-signal loads directly, thus eliminating the cost and size of external buffers for most applications. applications generally suited for the devices are: ? set point or offset trimming ? sensor calibration ? portable instrumentation (battery powered) ? motor control application examples include: ? dc set point or calibration ? decreasing output step size ? building a ?window? dac ? selectable gain and offset bipolar voltage output ? building programmable current source ? serial interface communication times ? software i2c interface reset sequence in the design of a system with the mcp47a1 devices, the following considerations should be taken into account: ? power supply considerations (noise) ? pcb area requirements ? connecting to i2c bus using pull-up resistors 8.1 dc set point or calibration a common application for the devices is a digitally-controlled set point and/or calibration of variable parameters, such as sensor offset or slope. for example, the mcp47a1 provides 64 output steps over the voltage reference range. if voltage reference is 1.65v, the lsb size is 1.65v / 64, or ~ 25.78 mv. applications that need accurate detection of an input threshold event often need several sources of error eliminated. use of comparators and operational amplifiers (op amps) with low offset and gain error can help achieve the desired accuracy, but in many applications, the input source variation is beyond the designer?s control. if the entire system can be calibrated after assembly in a controlled environment (like factory test), these sources of error are minimized, if not entirely eliminated. figure 8-1 illustrates this example circuit. equation 8-1 shows a quick estimation of the wiper value given the desired voltage trip (v trip ) point. figure 8-1: set point or threshold calibration. equation 8-1: estimating the wiper value (n) from the desired v trip v cc + v cc ? v o i 2 c? 2-wire v ref mcp47a1 v dd v out c 1 comp. v trip v sense v trip = v out = (n * v s ) ( v trip - v ref ) where: v s = v ref / 64 note: calculation does not take into account r fs and r zs resistors of the dac?s resistor ladder (see section 7.1 for additional information). n = v s
mcp47a1 ds25154a-page 48 ? 2012 microchip technology inc. 8.1.1 decreasing output step size due to the step voltage and output range of the mcp47a1, it may be desirable to reduce the step voltage while also modifying the range of the output. a common method to achieve this smaller step size is a voltage divider on the dac?s output. figure 8-2 illustrates this concept. equation 8-2 shows a quick estimation of the wiper value given the desired voltage trip (v trip ) point. for example, if r 1 = r 2 , then the v trip voltage range is from v ss to 1/2 * v ref . also at the v trip node, the step voltage is 1/2 the step voltage at the v out node. a bypass capacitor on the output of the voltage divider plays a critical function in attenuating the output noise of the dac and the induced noise from the environment. figure 8-2: example circuit of set point or threshold calibration. equation 8-2: v out and v trip estimations 8.1.2 building a ?window? dac when calibrating a set point or threshold of a sensor, typically only a small portion of the dac output range is utilized. if the lsb size is adequate enough to meet the application?s accuracy needs, the unused range is sacrificed without consequences. if greater accuracy is needed, then the output range will need to be reduced to increase the resolution around the desired threshold. if the threshold is not near v ref , 2 ? v ref , or v ss then creating a ?window? around the threshold has several advantages. one simple method to create this ?window? is to use a voltage divider network with a pull-up and pull-down resistor. figure 8-3 and figure 8- 4 illustrate this concept. figure 8-3: single-supply ?window? dac. equation 8-3: v out and v trip estimations note: the v out voltage can also be scaled by a resistor from the v ref pin to the system reference voltage. care should be taken with this implementation due to the 20% variation to the 20k ? typical resistance from the v ref pin to ground (r vref ). this variation in resistance directly effects the actual v out voltage. r 1 v cc + v cc ? v o i 2 c? 2-wire v ref mcp47a1 v dd v out r 2 c 1 comp. v trip v sense v out = n * v s v s = v ref / 64 r 2 r 1 + r 2 v trip = v out * r 1 v cc + v cc ? v o i 2 c? 2-wire v ref mcp47a1 v dd v out r 2 c 1 r 3 v cc + v cc ? r sense comp. v trip v out = n * v s v s = v ref / 64 v out * r 23 + v 23 * r 1 r 1 + r 23 v trip = r 1 r 23 v 23 v out v trip thevenin equivalent r 2 * r 3 r 2 + r 3 r 23 = (v cc+ * r 2 ) * (v cc- * r 3 ) r 2 + r 3 v 23 =
? 2012 microchip technology inc. ds25154a-page 49 mcp47a1 8.2 selectable gain and offset bipolar voltage output in some applications, control of the output range is desirable. figure 8-4 shows a circuit using a dac device to achieve a bipolar or single-supply application. this circuit is typically used for linearizing a sensor whose slope and offset varies. depending on the out- put range desired, resistor r 4 or resistor r 5 may not be required. equation 8-4 shows the calculation of the gain, while equation 8-5 shows the calculation of the v o voltage. this circuit can be simplified if the window range is limited (by removing either the r 4 or r 5 resistor). figure 8-5 shows a circuit for the case where the r 5 resistor is removed. resistors r 1 and r 2 control the gain, while resistors r 3 and r 4 shift the dac's output to a selected offset. equation 8-6 shows the calculation of the v o voltage. figure 8-4: bipolar voltage source with selectable gain and offset circuit. figure 8-5: simplified bipolar voltage source with selectable gain and offset circuit. equation 8-4: gain calculation equation 8-5: bipolar ?window? dac calculations equation 8-6: simplified bipolar ?window? dac calculations note: r4 can be tied to v dd , instead of v ss , if a higher offset is desired. r 3 v cc + v cc ? v o i 2 c? 2-wire v ref mcp47a1 v dd r 2 v out v in r 1 r 4 c 1 r 5 v oa+ v cc + v cc ? note: capacitor c 1 is recommended (0.1uf typical) r 3 v cc + v cc ? v o i 2 c? 2-wire v ref mcp47a1 v dd r 2 v out v in r 1 r 4 c 1 v oa+ note: capacitor c 1 is recommended (0.1uf typical) gain = r 2 r 1 if desired gain = 0.5, and r 1 is selected as 20 k ? then r 2 would need to be 10 k ? . offset adjust gain adjust v oa+ = (v out ? r 45 ) + (v 45 ? r 3 ) r 3 + r 45 v o = v oa+ ? ( 1 + ) - v in ? ( ) r 2 r 1 r 2 r 1 v out = n * v s (1) note 1: v out calculation does not take into account r fs and r zs resistors of the dac?s resistor ladder (see section 7.1 for additional information). v 45 = (v cc+ ? r 4 ) + (v cc- ? r 5 ) r 4 + r 5 r 45 = r 4 ? r 5 r 4 + r 5 v s = v ref 192 v oa+ = v out ? ( ) r 4 r 3 + r 4 v o = v oa+ ? ( 1 + ) - v in ? ( ) r 2 r 1 r 2 r 1 v out = n * v s note 1: v out calculation does not take into account r fs and r zs resistors of the dac?s resistor ladder (see section 7.1 for additional information).
mcp47a1 ds25154a-page 50 ? 2012 microchip technology inc. 8.3 building programmable current source figure 8-6 shows an example of building a programmable current source using a voltage follower. the current sensor resistor is used to convert the dac voltage output into a digitally-selectable current source. the smaller r sense is, the less power is dissipated across it. however, this also reduces the resolution that the current can be controlled. figure 8-6: digitally-controlled current source. 8.4 serial interface communication times table 8-1 shows time for each i 2 c serial interface command as well as the effective data update rate that can be supported by the digital interface (based on the two i 2 c serial interface frequencies). the continuous write command allows a higher data update frequency since for the fixed overhead more bytes are transferred. the serial interface performance, along with the v out output performance (such as slew rate), would be used to determine the application?s volatile dac register update rate. table 8-1: serial interface times / frequencies r sense i b load i l v cc + v cc ? v out i l v out r sense -------------- - ? ? 1 + ------------ - ? = i b i l ? ---- = ??? ? common-emitter current gain ? where v dd i 2 c? 2-wire v ref mcp47a1 v dd (or v ref ) command # of serial interface bits ( 1 ) example command time (s) effective data update frequency (khz) ( 2 ) # bytes transferred # of serial interface bits 100khz 400khz 100khz 400khz write single byte 29 1 29 290.0 72.5 3.4 13.8 write continuous bytes 20 + n * 9 5 65 650.0 162.5 7.7 30.8 read byte 39 1 39 390.0 97.5 2.6 10.3 note 1: includes the start or stop bits. 2: this is the command frequency multiplied by the number of bytes transferred.
? 2012 microchip technology inc. ds25154a-page 51 mcp47a1 8.5 software i 2 c interface reset sequence at times, it may become necessary to perform a software reset sequence to ensure the mcp47a1 device is in a correct and known i 2 c interface state. this technique only resets the i 2 c state machine. this is useful if the mcp47a1 device powers up in an incorrect state (due to excessive bus noise, etc), or if the master device is reset during communication. figure 8-7 shows the communication sequence to software reset the device. figure 8-7: software reset sequence format. the 1st start bit will cause the device to reset from a state in which it is expecting to receive data from the master device. in this mode, the device is monitoring the data bus in receive mode and can detect if the start bit forces an internal reset. the nine bits of ? 1 ? are used to force a reset of those devices that could not be reset by the previous start bit. this occurs only if the mcp47a1 is driving an a bit on the i 2 c bus, or is in output mode (from a read command) and is driving a data bit of ? 0 ? onto the i 2 c bus. in both of these cases, the previous start bit could not be generated due to the mcp47a1 holding the bus low. by sending out nine ? 1 ? bits, it is ensured that the device will see an a bit (the master device does not drive the i 2 c bus low to acknowledge the data sent by the mcp47a1), which also forces the mcp47a1 to reset. the 2nd start bit is sent to address the rare possibility of an erroneous write. this could occur if the master device was reset while sending a write command to the mcp47a1, and then as the master device returns to normal operation and issues a start condition, while the mcp47a1 is issuing an acknowledge. in this case, if the 2nd start bit is not sent (and the stop bit was sent) the mcp47a1 could initiate a write cycle. the stop bit terminates the current i 2 c bus activity. the mcp47a1 waits to detect the next start condition. this sequence does not effect any other i 2 c devices which may be on the bus, as they should disregard this as an invalid command. note: this technique should be supported by any i 2 c compliant device. the 24xxxx i 2 c serial eeprom devices support this technique, which is documented in an1028. s? 1 ?? 1 ?? 1 ?? 1 ?? 1 ?? 1 ?? 1 ?? 1 ? s p start bit nine bits of ? 1 ? start bit stop bit note: the potential for this erroneous write only occurs if the master device is reset while sending a write command to the mcp47a1.
mcp47a1 ds25154a-page 52 ? 2012 microchip technology inc. 8.6 design considerations 8.6.1 power supply considerations (noise) inductively-coupled ac transients and digital switching noise can degrade the input and output signal integrity, potentially masking the mcp47a1?s performance. careful board layout minimizes these effects and increases the signal-to-noise ratio (snr). multi-layer boards utilizing a low-inductance ground plane, isolated inputs, isolated outputs and proper decoupling are suggested. particularly harsh environments may require shielding of critical signals. the device?s power sources (v dd and v ref ) should be as clean as possible. any noise induced on the v dd and v ref signals can affect the dac performance. separate digital and analog ground planes are recommended. typical applications require a bypass capacitor in order to filter high-frequency noise on the v dd and v ref sig- nals. the noise can be induced onto the power supply?s traces or as a result of changes on the dac output. the bypass capacitor helps to minimize the effect of these noise sources on signal integrity. figure 8-8 illustrates an appropriate bypass strategy. in this example, the recommended bypass capacitor value is 0.1 f. this capacitor should be placed as close to the device power pin (v dd ) as possible (within 4mm). separate digital and analog ground planes are recommended. in this case, the v ss pin and the ground pins of the v dd capacitors should be terminated to the analog ground plane and v dd and v ss should reside on the analog plane. figure 8-9 shows an example of using two bypass capacitors (a 10 f tantalum capacitor and a 0.1 f ceramic capacitor) in parallel on the v dd line. these capacitors should be placed as close to the v dd pin as possible (within 4 mm). if the application circuit has separate digital and analog power supplies, the v dd and v ss pins of the device should reside on the analog plane. figure 8-8: typical microcontroller connections. figure 8-9: example mcp47a1 circuit. note: breadboards and wire-wrapped boards are not recommended. v dd v dd v ss v ss mcp47a1 0.1 f picmicro ? 0.1 f scl sda v out v ref microcontroller analog v dd 1 2 3 6 4 v dd scl sda v ss v out 5 r1 r2 to m c u r1 and r2 are i 2 c pull-up resistors: r1 and r2: 5k ? - 10 k ? for f scl = 100 khz to 400 khz c1: 0.1 f capacitor ceramic c2: 10 f capacitor tantalum c3: ~ 0.1 f optional to reduce noise in v out pin. c4: 0.1 f capacitor ceramic c5: 10 f capacitor tantalum c2 c1 mcp47a1 c3 optional output v ref c4 optional v ref c5
? 2012 microchip technology inc. ds25154a-page 53 mcp47a1 8.6.2 pcb area requirements in some applications, pcb area is a criteria for device selection. tab l e 8 - 2 shows the typical package dimensions and area for the different package options. table 8-2: package footprint ( 1 ) 8.6.3 pinout/footprint compatibility the mcp47a1 has a pinout and footprint compatibility to the mcp40d18 and mcp4018 devices. the mcp40d18/mcp4018?s w pin is analogous to the mcp47a1?s v out pin, while the mcp40d18/ mcp4018?s a pin is analogous to the mcp47a1?s v ref pin. the mcp40d18 and mcp47a1 share the same i 2 c command protocol structure. 8.6.4 connecting to i 2 c bus using pull-up resistors the scl and sda pins of the mcp47a1 devices are open-drain configurations. these pins require a pull-up resistor as shown in figure 8-9 . the pull-up resistor values (r1 and r2) for scl and sda pins depend on the operating speed (standard, fast, and high speed) and loading capacitance of the i 2 c bus line. a higher value of the pull-up resistor consumes less power, but increases the signal transition time (higher rc time constant) on the bus line. therefore, it can limit the bus operating speed. the lower resistor value, on the other hand, consumes higher power, but allows higher operating speed. if the bus line has higher capacitance due to long metal traces or multiple device connections to the bus line, a smaller pull-up resistor is needed to compensate the long rc time constant. the pull-up resistor is typically chosen between 1 k ?? and 10 k ?? ranges for standard and fast modes. 8.6.4.1 device connection test the user can test the presence of the device on the i 2 c bus line using a simple i 2 c command. this test can be achieved by checking an acknowledge response from the device after sending a read or write command. figure 8-10 shows an example with a read command. the steps are: a) set the r/w bit ?high? in the device?s address byte. b) check the ack bit of the address byte. if the device acknowledges (ack = 0 ) the command, then the device is connected, otherwise it is not connected. c) send stop bit. figure 8-10: i 2 c bus connection test. package package footprint pins type code dimensions (mm) area (mm 2 ) length width 6 sc70 lt 3.10 3.20 9.92 note 1: does not include recommended land pattern dimensions. dimensions are max values. 123456789 scl sda 11 0 1a2a1a0 1 start bit address byte address bits device code r/w stop bit device ack response
mcp47a1 ds25154a-page 54 ? 2012 microchip technology inc. notes:
? 2012 microchip technology inc. ds25154a-page 55 mcp47a1 9.0 development support 9.1 evaluation/demonstration boards the mcp47a1 devices do not have a dedicated evaluation or demonstration board. figure 9-1 shows the component connections to make an evaluation board using the sc70ev bond out pcb (order # sc70ev). this will allow the mcp47a1?s capabilities to be evaluated with the pickit? serial analyzer (order # dv164122). figure 9-1: sc70ev bond out pcb ? top layer and silk-screen. note: since the sc70ev is a generic board, the noise immunity of the board will not be optimal. if noise immunity is a require- ment, then a you will need to develop a custom pcb for the mcp47a1. this pcb would need to use good layout techniques to reduce noise coupling. 47a1 0 ? 0 ? c l & r l 0.1 f 1.0 f v ref (1) v out scl sda required components recommended components for noise filtering note 1: the v ref pin (p8) will need to be connected to a reference voltage source (such as v dd ). optional i 2 c bus pull up resistors (value may need to be adjusted for your system) 4.7 k ? 4.7 k ? vss vdd optional vout loading components (stacked), c l = 1 nf max and r l = 5 k ? max
mcp47a1 ds25154a-page 56 ? 2012 microchip technology inc. 9.2 technical documentation several additional technical documents are available to assist you in your design and development. these technical documents include application notes, technical briefs, and design guides. tab l e 9 - 1 shows some of these documents. table 9-1: technical documentation application note number title literature # an1326 using dac for ldmos amplifier bias control applications ds01326 ? signal chain design guide ds21825 ? analog solutions for automotive applications design guide ds01005
? 2012 microchip technology inc. ds25154a-page 57 mcp47a1 10.0 packaging information 10.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 6-lead sc-70 example part number code part number code mcp47a1t-a0e/lt bann mcp47a1t-a1e/lt bcnn bann
mcp47a1 ds25154a-page 58 ? 2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2012 microchip technology inc. ds25154a-page 59 mcp47a1 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp47a1 ds25154a-page 60 ? 2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2012 microchip technology inc. ds25154a-page 61 mcp47a1 appendix a: revision history revision a (august 2012) ? original release of this document.
mcp47a1 ds25154a-page 62 ? 2012 microchip technology inc. appendix b: terminology b.1 resolution the resolution is the number of dac output states that divide the full-scale range. for the 6-bit dac, the resolution is 2 6 , meaning the dac code ranges from 0 to 64. b.2 least significant bit (lsb) normally, this is thought of as the ideal voltage difference between two successive codes. this bit has the smallest value or weight of all bits in the register. for a given output voltage range, which is typically the voltage between the full-scale voltage and the zero- scale voltage (v out(fs) - v out(zs) ), it is divided by the resolution of the device ( equation b-1 ). equation b-1: lsb voltage calculation b.3 monotonic operation monotonic operation means that the device?s output voltage (v out ) increases with every one code step (lsb) change (from terminal b to terminal a). the v out voltage (v w voltage) is the sum of all the step voltages plus the voltage at zero-scale (v zs ). the zero-scale voltage is dependent on the resistance between the tap 0 point and the b terminal. figure b-1: v w (v out ). b.4 full-scale error (fse) the full-scale error (fse) is the difference between the ideal and measured dac output voltage with the wiper?s position set to its maximum (wiper code = 40h); see figure b-3 . full-scale error may also be thought of as the sum of the offset error plus gain error. see figure 2-9 through figure 2-12 for fse characterization graphs. equation b-2: full scale error b.5 zero-scale error (zse) the zero-scale error (zse) is the difference between the ideal and measured v out voltage with the wiper position set to its minimum (wiper code = 00h); see figure b-3 . the zero-scale error is the same as the offset error for this case (wiper code = 00h). equation b-3 shows how to calculate the zero scale error. see figure 2-13 through figure 2-16 for zse characterization graphs. equation b-3: zero scale error v lsb = v out(fs) - v out(zs) 2 n 2 n = 64 (mcp47a1) 0x40 0x3f 0x3e 0x03 0x02 0x01 0x00 wiper code voltage (v w ~= v out ) v w (@ tap) v s0 v s1 v s3 v s63 v s64 v w = v sn + v zs(@ tap 0) n = 0 n = ? fse = v ideal(@fs) - v out(@fs) v lsb where: fse is expressed in lsb v out(@fs) is the v out voltage when the dac register code is at full-scale. v ideal(@fs) is the ideal output voltage when the dac register code is at full-scale. v lsb is the delta voltage of one dac register code step (such as code 20h to code 21h). zse = v out(@zs) v lsb where: fse is expressed in lsb v out(@zs) is the v out voltage when the dac register code is at zero-scale. v lsb is the delta voltage of one dac register code step (such as code 20h to code 21h).
? 2012 microchip technology inc. ds25154a-page 63 mcp47a1 b.6 total unadjusted error the total unadjusted error is the difference between the ideal and measured v out voltage. typically, calibration of the output voltage is implemented to improve system performance. total unadjusted error can be calculated, see equation b-4 . equation b-4: total unadjusted error (lsb) see figure 2-17 through figure 2-20 for total unadjusted error characterization graphs. b.7 offset error the offset error (see figure b-2 ) is the deviation from zero voltage output when the volatile dac register value = 00h (zero scale voltage). this error affects all codes by the same amount. the offset error can be calibrated by software in application circuits. figure b-2: offset error. b.8 offset error drift the offset error drift is the variation in offset error due to a change in ambient temperature. the offset error drift is typically expressed in ppm/ o c. b.9 gain error the gain error (see figure b-3 ) is the difference between the actual full-scale output voltage, from the ideal output voltage of the dac transfer curve. the gain error is calculated after nullifying the offset error, or full scale error minus the offset error. the gain error indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. the gain error is usually expressed as percent of full-scale range (% of fsr) or in lsb. the gain error is not calibrated at the factory and most of the gain error is contributed by the output buffer (op amp) saturation. figure b-3: gain error and full- scale error example. b.10 gain error drift the gain error drift is the variation in gain error due to a change in ambient temperature. the gain error drift is typically expressed in ppm/ o c. error lsb = v ideal - v measured v lsb where: v ref is the voltage on the v ref pin. v measured is the v out voltage for the same dac register code as v ideal is calculated. v ideal = * dac code v ref 64 v lsb = v ref 64 analog output ideal transfer function actual transfer function dac input code 0 offset error (zse) analog output actual transfer function actual transfer function dac input code 0 gain error ideal transfer function after offset error is removed full-scale error zero-scale error
mcp47a1 ds25154a-page 64 ? 2012 microchip technology inc. b.11 integral nonlinearity (inl) the integral nonlinearity (inl) error is the maximum deviation of an actual transfer function from an ideal transfer function (straight line). in the mcp47a1, inl is calculated using two end points. the points used are zero-scale (00h) and full- scale - 1 (3fh). inl can be expressed as a percentage of full scale range (fsr) or in a fraction of an lsb. inl is also called relative accuracy. equation b-5 shows how to calculate the inl error in lsb and figure b-4 shows an example of inl accuracy. inl error for these devices is the maximum deviation between an actual code transition point and its corresponding ideal transition point after offset and gain errors have been removed. these endpoints are from 0x00 to 0x40 for the mcp47a1. refer to figure b- 4 . positive inl means higher v out voltage than ideal. negative inl means lower v out voltage than ideal. see figure 2-1 through figure 2-4 for inl character- ization graphs. equation b-5: inl error figure b-4: inl accuracy. b.12 differential nonlinearity (dnl) the differential nonlinearity (dnl) error (see figure b- 5 ) is the measure of step size between codes in actual transfer function. the ideal step size between codes is 1 lsb. a dnl error of zero would imply that every code is exactly 1 lsb wide. if the dnl error is less than 1 lsb, the dac guarantees monotonic output and no missing codes. the dnl error between any two adjacent codes is calculated as follows: dnl error is the measure of variations in code widths from the ideal code width. a dnl error of zero would imply that every code is exactly 1 lsb wide. see figure 2-5 through figure 2-8 for dnl character- ization graphs. equation b-6: dnl error figure b-5: dnl accuracy. inl lsb = v out - v ideal v s v ideal = v zs + ( v s * dac code ) v s = v (code=63) - v zs 63 111 110 101 100 011 010 001 000 wiper code actual transfer function inl < 0 ideal transfer function inl < 0 v out output voltage dnl lsb = v s - ( v (code = n) - v (code = n-1) ) v s v s = v (code=63) - v zs 63 111 110 101 100 011 010 001 000 wiper code actual transfer function ideal transfer function narrow code < 1 lsb wide code, > 1 lsb v out output voltage
? 2012 microchip technology inc. ds25154a-page 65 mcp47a1 b.13 settling time the settling time is the time delay required for the v out voltage to settle into its new output value. this time is measured from the start of code transition, to when the v out voltage is within the specified accuracy. in the mcp47a1, the settling time is a measure of the time delay until the v out voltage reaches within 0.5 lsb of its final value, when the volatile dac register changes from 40h to 50h. see figure 2-36 through figure 2-39 for settling time oscilloscope screen captures. b.14 major-code transition glitch major-code transition glitch is the impulse energy injected into the dac analog output when the code in the dac register changes state. it is normally specified as the area of the glitch in nv-sec, and is measured when the digital code is changed by 1 lsb at the major carry transition (example: wiper code changes from ? 011111? to ? 100000? , or from ? 100000? to ? 011111? ). b.15 digital feedthrough the digital feedthrough is the glitch that appears at the analog output caused by coupling from the digital input pins of the device. the area of the glitch is expressed in nv-sec, and is measured with a full scale change (example: all 0 s to all 1 s and vice versa) on the digital input pins. the digital feedthrough is measured when the dac is not being written to the output register. b.16 power-supply rejection ratio (psrr) psrr indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full-scale output of the dac. the v out is measured while the v dd is varied +/- 10%, and expressed in db or v/v. b.17 ratiometric temperature coefficient the ratiometric temperature coefficient quantifies the error in the ratio of the resistor setting (resistance from vref pin to wiper position (r vref-w ) and the wiper position to ground (r w-vss ) due to temperature drift. this error also includes the drift of the output driver over temperature. this is typically the critical error when using a dac. see figure 2-21 through figure 2-24 for tempco characterization graphs. b.18 absolute temperature coefficient the absolute temperature coefficient quantifies the error in the end-to-end output voltage (nominal output voltage v out ) due to temperature drift. for a dac, this error is typically not an issue, due to the ratiometric aspect of the output.
mcp47a1 ds25154a-page 66 ? 2012 microchip technology inc. notes:
? 2012 microchip technology inc. ds25154a-page 67 mcp47a1 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . device: mcp47a1t: 6-bit single dac with i 2 c interface (tape and reel) i 2 c slave address a0 = 5ch a1 = 7ch temperature range: e = -40c to +125c package: lt = plastic small outline transistor (sc70), 6-lead part no. x /xx package temperature range device examples: a) mcp47a1t-a0e/lt: 6-bit dac, sc70-6, address = 5ch, tape and reel b) mcp47a1t-a1e/lt: 6-bit dac, sc70-6, address = 7ch, tape and reel xxx i 2 c slave address
mcp47a1 ds25154a-page 68 ? 2012 microchip technology inc. notes:
? 2012 microchip technology inc. ds25154a-page 69 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, app lication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, total endurance, tsharc, uniwindriver, wiperlock and zena are trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2012, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-62076-491-6 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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